
//**************************************************
// include files
//**************************************************
`include "MAC_define.v"
`include "protocol_define.v"
`include "work_mode_define.v"
`define SRAM_2P_UHDE_SVT_MVT_ARM_DISABLE_DUMMY_CYCLE
//**************************************************
// timescale
//**************************************************
`timescale 1ns/100ps

//**************************************************
// top module define
//**************************************************
module Eth_1G_udp_top (
    input               clk_in                      , // osci clock (zeboard = 100MHz)
    input               reset                       , // reset pin
    input   [9:0]       ram_2p_cfg_register         ,
    
    //----------------------------------------------
    // PHY interface
    //----------------------------------------------
    // // reset "PHY"
    // output              phyrst_n                    , 

    // // RGMII receive channel
    // input               rgmii_rx_clk                ,
    // input               rgmii_rx_ctrl               ,
    // input   [3:0]       rgmii_rxd                   ,
    // // RGMII send channel
    // output              rgmii_tx_clk                ,
    // output              rgmii_tx_ctrl               ,
    // output  [3:0]       rgmii_txd                   ,
    output              mac_rx_rdy                  ,
    input   [31:0]      mac_rx_data                 ,
    input   [1:0]       mac_rx_mod                  ,
    input               mac_rx_sav                  ,
    input               mac_rx_val                  ,
    input               mac_rx_sop                  ,
    input               mac_rx_eop                  ,
    input   [10:0]      mac_rx_data_length          ,

    input               mac_tx_rdy                  ,
    output  [31:0]      mac_tx_data                 ,
    output  [1:0]       mac_tx_mod                  ,
    output              mac_tx_val                  ,
    output              mac_tx_sop                  ,
    output              mac_tx_eop                  ,

    //----------------------------------------------
    // NP interface
    //----------------------------------------------
    // 100 MHz clock for top use
    // output              clk_100M_top_use            ,
    // async FIFO clk
    // output              ACTION_fifo_clk             ,
    // async FIFO write
    output              ACTION_wr_en                ,
    output  [29:0]      ACTION_wr_order             ,
    output  [33:0]      ACTION_wr_addr              ,
    output  [31:0]      ACTION_wr_data              ,
    // async FIFO read
    output              ACTION_rd_en                ,
    input   [29:0]      ACTION_rd_order             ,
    input   [33:0]      ACTION_rd_addr              ,
    input   [31:0]      ACTION_rd_data              ,
    input               ACTION_rd_empty             ,

    // NP register in
    input   [47:0]      NP_MAC_address              ,
    input   [31:0]      NP_IP_address               ,
    input   [15:0]      NP_port_address             ,
    input   [31:0]      NP_action_addition            
) ;

/*
//**************************************************
// clock structure
//**************************************************
    wire clk_125M ;             // be used to   (1.) sync reset(including "phyrst_n") 
                                //              (2.) generate tx clk(in "clk_ctrl.v")
                                //              (3.) RGMII tx clk(in "rgmii_if.v")
    wire clk_100M ;             // be used as   (1.) system main clock
    wire clk_125M_90phase ;     // be used as   (1.) "rgmii_txc"
    
    wire dcm_locked ;           // keep "1" when output clock is ready

    //----------------------------------------------
    // generate clock
    //----------------------------------------------
    clk_gen inst_clk_gen(
        .RESET          (reset              ),
        .CLK_IN1_P      (clk_in             ),
        .CLK_IN1_N      (~clk_in            ),

        .CLK_OUT1       (clk_125M           ), // MAC clock
        .CLK_OUT2       (clk_100M           ), // main clock
        .CLK_OUT4       (clk_125M_90phase   ), // be used as "rgmii_txc"
        .CLK_OUT5       (clk_100M_top_use   ),
        .LOCKED         (dcm_locked         )
    ) ;
    assign ACTION_fifo_clk = clk_100M ;

//**************************************************
// delay control (be used in rgmii_if)
//**************************************************
    (* IODELAY_GROUP = "grp1" *)
`ifdef FPGA_ZEDBOARD_MODE
    IDELAYCTRL dlyctrl(
        .RDY            (        ),
        .REFCLK         (clk_100M),
        .RST            (Reset   )
    );
`elsif FPGA_VCU13PBOARD_MODE
    IDELAYCTRL #(
      .SIM_DEVICE("ULTRASCALE")  // Must be set to "ULTRASCALE" 
   )
    dlyctrl (
      .RDY              (),         // 1-bit output: Ready output
      .REFCLK           (clk_100M), // 1-bit input: Reference clock input
      .RST              (Reset)     // 1-bit input: Active high reset input. Asynchronous assert, synchronous deassert to REFCLK.
   );
`endif
*/

//**************************************************
// Subsystem 
//**************************************************
    //----------------------------------------------
    // MAC wire declare
    //----------------------------------------------
    // rx channel
    // wire            mac_rx_rdy ;
    // wire [31:0]     mac_rx_data ;
    // wire [1:0]      mac_rx_mod ;
    // wire            mac_rx_sav ;
    // wire            mac_rx_val ;
    // wire            mac_rx_sop ;
    // wire            mac_rx_eop ;
    // wire [5:0]      mac_rx_err ;
    // wire [10:0]     mac_rx_data_length ;
    // // tx channel
    // wire            mac_tx_rdy ;
    // wire [31:0]     mac_tx_data ;
    // wire [1:0]      mac_tx_mod ;
    // wire            mac_tx_sav ;
    // wire            mac_tx_val ;
    // wire            mac_tx_sop ;
    // wire            mac_tx_eop ;
    //----------------------------------------------
    // MAC instance
    //----------------------------------------------
    // MAC_top_top inst_MAC(
    //     .Reset              (reset              ),
    //     .phyrst_n           (phyrst_n           ),
    //     //clock block       
    //     .Clk_user           (clk_100M           ),
    //     .Clk_125M           (clk_125M           ),
    //     .Clk90              (clk_125M_90phase   ),
    //     .dcm_locked         (dcm_locked         ),
    //     //RGMII interface
    //     .rgmii_rx_clk       (rgmii_rx_clk       ),
    //     .rgmii_rxd          (rgmii_rxd          ),
    //     .rgmii_rx_ctl       (rgmii_rx_ctrl      ),
    //     .rgmii_tx_clk       (rgmii_tx_clk       ),
    //     .rgmii_txd          (rgmii_txd          ),
    //     .rgmii_tx_ctl       (rgmii_tx_ctrl      ),
        
    //     // rx channel
    //     .ff_rx_rdy          (mac_rx_rdy         ), // input
    //     .ff_rx_data         (mac_rx_data        ),
    //     .ff_rx_mod          (mac_rx_mod         ),
    //     .ff_rx_dsav         (mac_rx_sav         ),
    //     .ff_rx_dval         (mac_rx_val         ),
    //     .ff_rx_sop          (mac_rx_sop         ),
    //     .ff_rx_eop          (mac_rx_eop         ),
    //     .rx_err             (mac_rx_err         ), // no use
    //     .frame_length       (mac_rx_data_length ),
    //     // tx channel
    //     .ff_tx_rdy          (mac_tx_rdy         ),
    //     .ff_tx_data         (mac_tx_data        ), // input
    //     .ff_tx_mod          (mac_tx_mod         ), // input
    //     .ff_tx_wren         (mac_tx_val         ), // input
    //     .ff_tx_sop          (mac_tx_sop         ), // input
    //     .ff_tx_eop          (mac_tx_eop         ), // input
    //     .ff_tx_err          (1'b0               ), // input
    //     .ff_tx_septy        (                   ),
    //     // FIFO data counter 
    //     .Fifo_data_count    (                   )
    // ) ;

    wire clk_100M ;
    assign clk_100M = clk_in ;
    //----------------------------------------------
    // bus convert signal declare
    //----------------------------------------------
    // rx channel
    wire            unpack_rdy ;
    wire [127:0]    unpack_data ;
    wire [3:0]      unpack_mod ;
    wire            unpack_sav ;
    wire            unpack_val ;
    wire            unpack_sop ;
    wire            unpack_eop ;
    //----------------------------------------------
    // rx bus convert instance 
    //----------------------------------------------
    rx_bus_convert #(
        .IN_MOD_WIDTH               (`BUS_CONVERT_IN_MOD_WIDTH          ) ,
        .IN_DATA_WIDTH              (`BUS_CONVERT_IN_DATA_WIDTH         ) ,
        .IN_BYTE_PER_PHASE          (`BUS_CONVERT_IN_BYTE_PER_CYCLE     ) ,
        .OUT_MOD_WIDTH              (`BUS_CONVERT_OUT_MOD_WIDTH         ) ,
        .OUT_DATA_WIDTH             (`BUS_CONVERT_OUT_DATA_WIDTH        )
        )
    inst_rx_bus_convert(
        .clk                        (clk_100M               ) ,
        .rst_n                      ( (!reset)              ) ,
        .ram_2p_cfg_register        (ram_2p_cfg_register    ) ,
        // connect with MAC rx_channel
        .bus_convert_rx_rdy         (mac_rx_rdy             ) ,
        .bus_convert_rx_data        (mac_rx_data            ) ,
        .bus_convert_rx_mod         (mac_rx_mod             ) ,
        .bus_convert_rx_sav         (mac_rx_sav             ) , // no use
        .bus_convert_rx_val         (mac_rx_val             ) ,
        .bus_convert_rx_sop         (mac_rx_sop             ) ,
        .bus_convert_rx_eop         (mac_rx_eop             ) ,
        .bus_convert_rx_err         (6'b0                   ) , // no use
        .rx_frame_length            (mac_rx_data_length     ) ,
        // connect with unpack
        .unpack_rdy                 (unpack_rdy             ) ,
        .unpack_data                (unpack_data            ) ,
        .unpack_mod                 (unpack_mod             ) ,
        .unpack_sav                 (unpack_sav             ) ,
        .unpack_val                 (unpack_val             ) ,
        .unpack_sop                 (unpack_sop             ) ,
        .unpack_eop                 (unpack_eop             )
    ) ;



    //----------------------------------------------
    // unpack module signal declare
    //----------------------------------------------
    // dedecated protocol channel
    wire    [47:0]                  DATALINK_src_mac ;
    wire    [47:0]                  DATALINK_dst_mac ;
    // ARP channel
    wire                            ARP_enable      ;
    wire    [15:0]                  ARP_hard_type   ;
    wire    [15:0]                  ARP_prot_type   ;
    wire    [7:0]                   ARP_hard_len    ;
    wire    [7:0]                   ARP_prot_len    ;
    wire    [15:0]                  ARP_op          ;
    wire    [47:0]                  ARP_src_mac     ;
    wire    [31:0]                  ARP_src_ip      ;
    wire    [47:0]                  ARP_dst_mac     ;
    wire    [31:0]                  ARP_dst_ip      ;    
    // IP channel
    wire                            UDP_rdy         ;
    wire    [127:0]                 IPv4_payload    ;
    wire    [3:0]                   IPv4_mod        ;
    wire                            IPv4_sav        ;
    wire                            IPv4_val        ;
    wire                            IPv4_sop        ;
    wire                            IPv4_eop        ;
    wire    [31:0]                  IPv4_dst_IP     ;
    wire    [31:0]                  IPv4_src_IP     ;
    //----------------------------------------------
    // instance
    //----------------------------------------------
    unpack #(
        .IN_DATA_WIDTH  (`BUS_CONVERT_OUT_DATA_WIDTH) ,
        .IN_MOD_WIDTH   (`BUS_CONVERT_OUT_MOD_WIDTH)
        )
    inst_unpack(
        .clk                        (clk_100M               ) ,
        .rst_n                      ( (!reset)              ) ,
        // unpack
        .unpack_rdy                 (unpack_rdy             ) ,
        .unpack_data                (unpack_data            ) ,
        .unpack_mod                 (unpack_mod             ) ,
        .unpack_sav                 (unpack_sav             ) ,
        .unpack_val                 (unpack_val             ) ,
        .unpack_sop                 (unpack_sop             ) ,
        .unpack_eop                 (unpack_eop             ) ,
        // ARP deal module
        .ARP_enable                 (ARP_enable             ) ,
        .ARP_hard_type              (ARP_hard_type          ) ,
        .ARP_prot_type              (ARP_prot_type          ) ,
        .ARP_hard_len               (ARP_hard_len           ) ,
        .ARP_prot_len               (ARP_prot_len           ) ,
        .ARP_op                     (ARP_op                 ) ,
        .ARP_src_mac                (ARP_src_mac            ) ,
        .ARP_src_ip                 (ARP_src_ip             ) ,
        .ARP_dst_mac                (ARP_dst_mac            ) ,
        .ARP_dst_ip                 (ARP_dst_ip             ) ,
        // UDP deal module
        .UDP_rdy                    (UDP_rdy                ) ,
        .IPv4_payload               (IPv4_payload           ) ,
        .IPv4_mod                   (IPv4_mod               ) ,
        .IPv4_sav                   (IPv4_sav               ) ,
        .IPv4_val                   (IPv4_val               ) ,
        .IPv4_sop                   (IPv4_sop               ) ,
        .IPv4_eop                   (IPv4_eop               ) ,
        .IPv4_dst_IP                (IPv4_dst_IP            ) ,
        .IPv4_src_IP                (IPv4_src_IP            ) ,
        // "data link" layer MAC field
        .DATALINK_src_mac           (DATALINK_src_mac       ) ,
        .DATALINK_dst_mac           (DATALINK_dst_mac       )
    ) ;



    //----------------------------------------------
    // ARP deal module signal declare
    //----------------------------------------------
    wire                            ARP_gen_enable ;
    wire    [15:0]                  ARP_gen_hard_type ;
    wire    [15:0]                  ARP_gen_prot_type ;
    wire    [7:0]                   ARP_gen_hard_len ;
    wire    [7:0]                   ARP_gen_prot_len ;
    wire    [15:0]                  ARP_gen_op ;
    wire    [47:0]                  ARP_gen_src_mac ;
    wire    [31:0]                  ARP_gen_src_ip ;
    wire    [47:0]                  ARP_gen_dst_mac ;
    wire    [31:0]                  ARP_gen_dst_ip ;
    wire    [47:0]                  DATALINK_gen_src_mac ;
    wire    [47:0]                  DATALINK_gen_dst_mac ;
    //----------------------------------------------
    // ARP deal module instance
    //----------------------------------------------
    ARP_deal #(
        .ARP_SET_HARD_TYPE(`ARP_SET_HARD_TYPE   ) ,
        .ARP_SET_PROT_TYPE(`ARP_SET_PROT_TYPE   ) ,
        .ARP_SET_HARD_LEN (`ARP_SET_HARD_LEN    ) ,
        .ARP_SET_PROT_LEN (`ARP_SET_PROT_LEN    ) ,
        .ARP_SET_OP       (`ARP_SET_OP          ) ,
        .ARP_GEN_HARD_TYPE(`ARP_GEN_HARD_TYPE   ) ,
        .ARP_GEN_PROT_TYPE(`ARP_GEN_PROT_TYPE   ) ,
        .ARP_GEN_HARD_LEN (`ARP_GEN_HARD_LEN    ) ,
        .ARP_GEN_PROT_LEN (`ARP_GEN_PROT_LEN    ) ,
        .ARP_GEN_OP       (`ARP_GEN_OP          )
        )
    inst_ARP_deal (
        .clk                        (clk_100M               ) ,
        .rst_n                      ( (!reset)              ) ,
        // unpack module
        .ARP_enable                 (ARP_enable             ) ,
        .ARP_hard_type              (ARP_hard_type          ) ,
        .ARP_prot_type              (ARP_prot_type          ) ,
        .ARP_hard_len               (ARP_hard_len           ) ,
        .ARP_prot_len               (ARP_prot_len           ) ,
        .ARP_op                     (ARP_op                 ) ,
        .ARP_src_mac                (ARP_src_mac            ) ,
        .ARP_src_ip                 (ARP_src_ip             ) ,
        .ARP_dst_mac                (ARP_dst_mac            ) ,
        .ARP_dst_ip                 (ARP_dst_ip             ) ,
        .DATALINK_src_mac           (DATALINK_src_mac       ) ,
        .DATALINK_dst_mac           (DATALINK_dst_mac       ) ,
        // gen module
        .ARP_gen_enable             (ARP_gen_enable         ) ,
        .ARP_gen_hard_type          (ARP_gen_hard_type      ) ,
        .ARP_gen_prot_type          (ARP_gen_prot_type      ) ,
        .ARP_gen_hard_len           (ARP_gen_hard_len       ) ,
        .ARP_gen_prot_len           (ARP_gen_prot_len       ) ,
        .ARP_gen_op                 (ARP_gen_op             ) ,
        .ARP_gen_src_mac            (ARP_gen_src_mac        ) ,
        .ARP_gen_src_ip             (ARP_gen_src_ip         ) ,
        .ARP_gen_dst_mac            (ARP_gen_dst_mac        ) ,
        .ARP_gen_dst_ip             (ARP_gen_dst_ip         ) ,
        .DATALINK_gen_src_mac       (DATALINK_gen_src_mac   ) ,
        .DATALINK_gen_dst_mac       (DATALINK_gen_dst_mac   ) ,
        // register
        .NP_MAC_address             (NP_MAC_address         ) ,
        .NP_IP_address              (NP_IP_address          )
    ) ;



    //----------------------------------------------
    // ARP response generator module signal declare
    //----------------------------------------------
    wire                        ARP_frame_rdy ;
    wire    [127:0]             ARP_frame_data ;
    wire    [3:0]               ARP_frame_mod ;
    wire                        ARP_frame_sav ;
    wire                        ARP_frame_val ;
    wire                        ARP_frame_sop ;
    wire                        ARP_frame_eop ;
    //----------------------------------------------
    // ARP response generator module instance
    //----------------------------------------------
    arp_gen inst_arp_gen(
        .clk                        (clk_100M               ) ,
        .rst_n                      ( (!reset)              ) ,
        // arp deal module
        .ARP_gen_enable             (ARP_gen_enable         ) ,
        .ARP_gen_hard_type          (ARP_gen_hard_type      ) ,
        .ARP_gen_prot_type          (ARP_gen_prot_type      ) ,
        .ARP_gen_hard_len           (ARP_gen_hard_len       ) ,
        .ARP_gen_prot_len           (ARP_gen_prot_len       ) ,
        .ARP_gen_op                 (ARP_gen_op             ) ,
        .ARP_gen_src_mac            (ARP_gen_src_mac        ) ,
        .ARP_gen_src_ip             (ARP_gen_src_ip         ) ,
        .ARP_gen_dst_mac            (ARP_gen_dst_mac        ) ,
        .ARP_gen_dst_ip             (ARP_gen_dst_ip         ) ,
        .DATALINK_gen_src_mac       (DATALINK_gen_src_mac   ) ,
        .DATALINK_gen_dst_mac       (DATALINK_gen_dst_mac   ) ,
        // arbiter module
        .arp_rx_rdy                 (ARP_frame_rdy          ) ,
        // .arp_ready                  (                       ) ,
        .arp_tx_data                (ARP_frame_data         ) ,
        .arp_tx_mod                 (ARP_frame_mod          ) ,
        .arp_tx_sav                 (ARP_frame_sav          ) ,
        .arp_tx_val                 (ARP_frame_val          ) ,
        .arp_tx_sop                 (ARP_frame_sop          ) ,
        .arp_tx_eop                 (ARP_frame_eop          ) 
        // .arp_tx_err                 (                       )
    ) ;



    //----------------------------------------------
    // UDP deal module signal declare
    //----------------------------------------------
    // frame info FIFO channel
    wire                            fifo_wr_en ;
    wire    [47:0]                  DATALINK_dst_mac_fifo ;
    wire    [47:0]                  DATALINK_src_mac_fifo ;
    wire    [31:0]                  NETWORK_src_IP_fifo ;
    wire    [31:0]                  NETWORK_dst_IP_fifo ;
    wire    [15:0]                  TRANSPORT_src_port_fifo ;
    wire    [15:0]                  TRANSPORT_dst_port_fifo ;
    // excute channel
    wire                            PROTOCOL_rdy ;
    wire    [127:0]                 PROTOCOL_data ;
    wire    [3:0]                   PROTOCOL_mod ;
    wire                            PROTOCOL_sav ;
    wire                            PROTOCOL_val ;
    wire                            PROTOCOL_sop ;
    wire                            PROTOCOL_eop ;
    //----------------------------------------------
    // UDP deal module instance
    //----------------------------------------------
    UDP_deal #(
        .IN_DATA_WIDTH  (`BUS_CONVERT_OUT_DATA_WIDTH) ,
        .IN_MOD_WIDTH   (`BUS_CONVERT_OUT_MOD_WIDTH)
        )
    inst_UDP_deal(
        .clk                        (clk_100M               ) ,
        .rst_n                      ( (!reset)              ) ,
        // unpack module
        .UDP_rdy                    (UDP_rdy                ) ,
        .IPv4_payload               (IPv4_payload           ) ,
        .IPv4_mod                   (IPv4_mod               ) ,
        .IPv4_sav                   (IPv4_sav               ) ,
        .IPv4_val                   (IPv4_val               ) ,
        .IPv4_sop                   (IPv4_sop               ) ,
        .IPv4_eop                   (IPv4_eop               ) ,
        // extracted field
        .IPv4_dst_IP                (IPv4_dst_IP            ) ,
        .IPv4_src_IP                (IPv4_src_IP            ) ,
        .DATALINK_src_mac           (DATALINK_src_mac       ) ,
        .DATALINK_dst_mac           (DATALINK_dst_mac       ) ,
        // execute module
        .PROTOCOL_check_rdy         (PROTOCOL_rdy           ) ,
        .PROTOCOL_check_data        (PROTOCOL_data          ) ,
        .PROTOCOL_check_mod         (PROTOCOL_mod           ) ,
        .PROTOCOL_check_sav         (PROTOCOL_sav           ) ,
        .PROTOCOL_check_val         (PROTOCOL_val           ) ,
        .PROTOCOL_check_sop         (PROTOCOL_sop           ) ,
        .PROTOCOL_check_eop         (PROTOCOL_eop           ) ,
        // send to tx channel FIFO
        .fifo_wr_en                 (fifo_wr_en             ) ,
        .DATALINK_dst_mac_fifo      (DATALINK_dst_mac_fifo  ) ,
        .DATALINK_src_mac_fifo      (DATALINK_src_mac_fifo  ) ,
        .NETWORK_src_IP_fifo        (NETWORK_src_IP_fifo    ) ,
        .NETWORK_dst_IP_fifo        (NETWORK_dst_IP_fifo    ) ,
        .TRANSPORT_src_port_fifo    (TRANSPORT_src_port_fifo) ,
        .TRANSPORT_dst_port_fifo    (TRANSPORT_dst_port_fifo) ,

        // NP config register
        .NP_MAC_address             (NP_MAC_address         ) ,
        .NP_IP_address              (NP_IP_address          ) ,
        .NP_port_address            (NP_port_address        )
    ) ;



    //----------------------------------------------
    // Frame info FIFO signal declare
    //----------------------------------------------
    wire                            fifo_rd_en ;
    wire    [47:0]                  rd_DATALINK_dst_mac_fifo ;
    wire    [47:0]                  rd_DATALINK_src_mac_fifo ;
    wire    [31:0]                  rd_NETWORK_src_IP_fifo ;
    wire    [31:0]                  rd_NETWORK_dst_IP_fifo ;
    wire    [15:0]                  rd_TRANSPORT_src_port_fifo ;
    wire    [15:0]                  rd_TRANSPORT_dst_port_fifo ;
    //----------------------------------------------
    // Frame info FIFO instance
    //----------------------------------------------
    assemble_frame_info_fifo inst_assemble_frame_info_fifo (
        .clk                        (clk_100M                   ) ,
        .rst                        (reset                      ) ,
        .ram_2p_cfg_register        (ram_2p_cfg_register        ) ,
        // write channel
        .fifo_wr_en                 (fifo_wr_en                 ) ,
        .DATALINK_dst_mac_fifo      (DATALINK_dst_mac_fifo      ) ,
        .DATALINK_src_mac_fifo      (DATALINK_src_mac_fifo      ) ,
        .NETWORK_src_IP_fifo        (NETWORK_src_IP_fifo        ) ,
        .NETWORK_dst_IP_fifo        (NETWORK_dst_IP_fifo        ) ,
        .TRANSPORT_src_port_fifo    (TRANSPORT_src_port_fifo    ) ,
        .TRANSPORT_dst_port_fifo    (TRANSPORT_dst_port_fifo    ) ,
        // read channel
        .fifo_rd_en                 (fifo_rd_en                 ) ,
        .rd_DATALINK_dst_mac_fifo   (rd_DATALINK_dst_mac_fifo   ) ,
        .rd_DATALINK_src_mac_fifo   (rd_DATALINK_src_mac_fifo   ) ,
        .rd_NETWORK_src_IP_fifo     (rd_NETWORK_src_IP_fifo     ) ,
        .rd_NETWORK_dst_IP_fifo     (rd_NETWORK_dst_IP_fifo     ) ,
        .rd_TRANSPORT_src_port_fifo (rd_TRANSPORT_src_port_fifo ) ,
        .rd_TRANSPORT_dst_port_fifo (rd_TRANSPORT_dst_port_fifo )
    ) ;



    //----------------------------------------------
    // excute module instance
    //----------------------------------------------
    execute #(
        .IN_DATA_WIDTH      (`BUS_CONVERT_OUT_DATA_WIDTH) ,
        .IN_MOD_WIDTH       (`BUS_CONVERT_OUT_MOD_WIDTH ) ,
        .OUT_ORDER_WIDTH    (`PROTOCOL_ORDER_WIDTH      ) ,
        .OUT_ADDR_WIDTH     (`PROTOCOL_ADDR_WIDTH       ) ,
        .OUT_DATA_WIDTH     (`PROTOCOL_DATA_WIDTH       )
        )
    inst_execute (
        .clk                        (clk_100M               ) ,
        .rst_n                      ( (!reset)              ) ,
        // UDP deal module
        .PROTOCOL_rdy               (PROTOCOL_rdy           ) ,
        .PROTOCOL_data              (PROTOCOL_data          ) ,
        .PROTOCOL_mod               (PROTOCOL_mod           ) ,
        .PROTOCOL_sav               (PROTOCOL_sav           ) ,
        .PROTOCOL_val               (PROTOCOL_val           ) ,
        .PROTOCOL_sop               (PROTOCOL_sop           ) ,
        .PROTOCOL_eop               (PROTOCOL_eop           ) ,
        // NP action addition
        .NP_action_addition         (NP_action_addition     ) ,
        // async FIFO out
        .ACTION_wren                (ACTION_wr_en           ) ,
        .ACTION_order               (ACTION_wr_order        ) ,
        .ACTION_addr                (ACTION_wr_addr         ) ,
        .ACTION_data                (ACTION_wr_data         )
    ) ;



    //----------------------------------------------
    // protocol response signal declare
    //----------------------------------------------
    wire                            protocol_gen_rdy        ;
    wire                            protocol_start_trans    ;
    wire    [95:0]                  protocol_gen_data       ;
    wire                            protocol_gen_sav        ;
    wire                            protocol_gen_val        ;
    wire                            protocol_gen_sop        ;
    wire                            protocol_gen_eop        ;
    wire                            convert_frame_info      ;

    //----------------------------------------------
    // protocol response module instance
    //----------------------------------------------
    protocol_response #(
        .IN_DATA_WIDTH      (`BUS_CONVERT_OUT_DATA_WIDTH    ) ,
        .OUT_ORDER_WIDTH    (`PROTOCOL_ORDER_WIDTH          ) ,
        .OUT_ADDR_WIDTH     (`PROTOCOL_ADDR_WIDTH           ) ,
        .OUT_DATA_WIDTH     (`PROTOCOL_DATA_WIDTH           )
        )
    inst_protocol_response (
        .clk                        (clk_100M               ) ,
        .rst_n                      ( (!reset)              ) ,
        // async FIFO read
        .ACTION_rd_en               (ACTION_rd_en           ) ,
        .ACTION_rd_order            (ACTION_rd_order        ) ,
        .ACTION_rd_addr             (ACTION_rd_addr         ) ,
        .ACTION_rd_data             (ACTION_rd_data         ) ,
        .ACTION_rd_empty            (ACTION_rd_empty        ) ,
        // generate UDP frame
        .protocol_gen_rdy           (protocol_gen_rdy       ) ,
        .protocol_start_trans       (protocol_start_trans   ) ,
        .protocol_gen_data          (protocol_gen_data      ) ,
        .protocol_gen_sav           (protocol_gen_sav       ) ,
        .protocol_gen_val           (protocol_gen_val       ) ,
        .protocol_gen_sop           (protocol_gen_sop       ) ,
        .protocol_gen_eop           (protocol_gen_eop       ) ,
        .convert_frame_info         (convert_frame_info     )
    ) ;
    assign fifo_rd_en = convert_frame_info ;


    //----------------------------------------------
    // UDP frame generator declare
    //----------------------------------------------
    wire                        UDP_frame_rdy ;
    wire    [127:0]             UDP_frame_data ;
    wire    [3:0]               UDP_frame_mod ;
    wire                        UDP_frame_sav ;
    wire                        UDP_frame_val ;
    wire                        UDP_frame_sop ;
    wire                        UDP_frame_eop ;
    //----------------------------------------------
    // UDP frame generator instance
    //----------------------------------------------
    tx_frame_generator inst_tx_frame_generator(
        .clk                        (clk_100M               ) ,
        .rst_n                      ( (!reset)              ) ,
        .ram_2p_cfg_register        (ram_2p_cfg_register    ) ,
        // response module
        .protocol_gen_rdy           (protocol_gen_rdy       ) ,
        .protocol_start_trans       (protocol_start_trans   ) ,
        .protocol_gen_data          (protocol_gen_data      ) ,
        .protocol_gen_sav           (protocol_gen_sav       ) ,
        .protocol_gen_val           (protocol_gen_val       ) ,
        .protocol_gen_sop           (protocol_gen_sop       ) ,
        .protocol_gen_eop           (protocol_gen_eop       ) ,
        .convert_frame_info         (convert_frame_info     ) ,
        // frame info FIFO
        .rd_DATALINK_dst_mac_fifo   (rd_DATALINK_dst_mac_fifo   ) ,
        .rd_DATALINK_src_mac_fifo   (rd_DATALINK_src_mac_fifo   ) ,
        .rd_NETWORK_src_IP_fifo     (rd_NETWORK_src_IP_fifo     ) ,
        .rd_NETWORK_dst_IP_fifo     (rd_NETWORK_dst_IP_fifo     ) ,
        .rd_TRANSPORT_src_port_fifo (rd_TRANSPORT_src_port_fifo ) ,
        .rd_TRANSPORT_dst_port_fifo (rd_TRANSPORT_dst_port_fifo ) ,
        // arbiter module
        .UDP_frame_rdy              (UDP_frame_rdy          ) ,
        .UDP_frame_data             (UDP_frame_data         ) ,
        .UDP_frame_mod              (UDP_frame_mod          ) ,
        .UDP_frame_sav              (UDP_frame_sav          ) ,
        .UDP_frame_val              (UDP_frame_val          ) ,
        .UDP_frame_sop              (UDP_frame_sop          ) ,
        .UDP_frame_eop              (UDP_frame_eop          )
    ) ;



    //----------------------------------------------
    // arbiter signal declare
    //----------------------------------------------
    wire                        tx_bus_convert_rdy ;
    wire    [127:0]             tx_bus_convert_data ;
    wire    [3:0]               tx_bus_convert_mod ;
    wire                        tx_bus_convert_sav ;
    wire                        tx_bus_convert_val ;
    wire                        tx_bus_convert_sop ;
    wire                        tx_bus_convert_eop ;
    //----------------------------------------------
    // arbiter module instance
    //----------------------------------------------
    tx_frame_aribiter #(
        .IN_DATA_WIDTH  (`BUS_CONVERT_OUT_DATA_WIDTH) ,
        .IN_MOD_WIDTH   (`BUS_CONVERT_OUT_MOD_WIDTH)
        )
    inst_tx_frame_arbiter (
        .clk                        (clk_100M               ) ,
        .rst_n                      ( (!reset)              ) ,
        // ARP frame generator
        .ARP_frame_rdy              (ARP_frame_rdy          ) ,
        .ARP_frame_data             (ARP_frame_data         ) ,
        .ARP_frame_mod              (ARP_frame_mod          ) ,
        .ARP_frame_sav              (ARP_frame_sav          ) ,
        .ARP_frame_val              (ARP_frame_val          ) ,
        .ARP_frame_sop              (ARP_frame_sop          ) ,
        .ARP_frame_eop              (ARP_frame_eop          ) ,
        // UDP frame generator
        .UDP_frame_rdy              (UDP_frame_rdy          ) ,
        .UDP_frame_data             (UDP_frame_data         ) ,
        .UDP_frame_mod              (UDP_frame_mod          ) ,
        .UDP_frame_sav              (UDP_frame_sav          ) ,
        .UDP_frame_val              (UDP_frame_val          ) ,
        .UDP_frame_sop              (UDP_frame_sop          ) ,
        .UDP_frame_eop              (UDP_frame_eop          ) ,

        // 128 to 32 bus convert
        .tx_bus_convert_rdy         (tx_bus_convert_rdy     ) ,
        .tx_bus_convert_data        (tx_bus_convert_data    ) ,
        .tx_bus_convert_mod         (tx_bus_convert_mod     ) ,
        .tx_bus_convert_sav         (tx_bus_convert_sav     ) ,
        .tx_bus_convert_val         (tx_bus_convert_val     ) ,
        .tx_bus_convert_sop         (tx_bus_convert_sop     ) ,
        .tx_bus_convert_eop         (tx_bus_convert_eop     )
    ) ;



    //----------------------------------------------
    // tx bus convert instance 
    //----------------------------------------------
    tx_bus_convert #(
        .IN_MOD_WIDTH               (`BUS_CONVERT_OUT_MOD_WIDTH         ) ,
        .IN_DATA_WIDTH              (`BUS_CONVERT_OUT_DATA_WIDTH        ) ,
        .OUT_BYTE_PER_PHASE         (`BUS_CONVERT_IN_BYTE_PER_CYCLE     ) ,
        .OUT_MOD_WIDTH              (`BUS_CONVERT_IN_MOD_WIDTH          ) ,
        .OUT_DATA_WIDTH             (`BUS_CONVERT_IN_DATA_WIDTH         )
        )
    inst_tx_bus_convert (
        .clk                        (clk_100M               ) ,
        .rst_n                      ( (!reset)              ) ,
        .ram_2p_cfg_register        (ram_2p_cfg_register    ) ,
        // arbiter module
        .tx_bus_convert_rdy         (tx_bus_convert_rdy     ) ,    
        .tx_bus_convert_data        (tx_bus_convert_data    ) ,
        .tx_bus_convert_mod         (tx_bus_convert_mod     ) ,
        .tx_bus_convert_sav         (tx_bus_convert_sav     ) ,
        .tx_bus_convert_val         (tx_bus_convert_val     ) ,
        .tx_bus_convert_sop         (tx_bus_convert_sop     ) ,
        .tx_bus_convert_eop         (tx_bus_convert_eop     ) ,
        // MAC tx channel
        .mac_tx_rdy                 (mac_tx_rdy             ) ,
        .mac_tx_data                (mac_tx_data            ) ,
        .mac_tx_mod                 (mac_tx_mod             ) ,
        .mac_tx_sav                 (                       ) ,
        .mac_tx_val                 (mac_tx_val             ) ,
        .mac_tx_sop                 (mac_tx_sop             ) ,
        .mac_tx_eop                 (mac_tx_eop             )
    ) ;

endmodule
